The present invention relates to electronic circuit, and more particularly, to charge pump circuits.
A clock and data recovery (CDR) circuit is used in some communications systems, such as high-speed backplane, chip-to-chip, and line-side systems. A periodic clock signal is embedded in a data stream on the transmitting end of the system. A CDR circuit recovers the periodic clock signal from the data stream on the receiving end of the system. CDR functionality allows for higher transmission speeds, ensures that the data and clock signals are in phase, and relieves board trace routing restrictions.
The Stratix® II GX field programmable gate array manufactured by Altera Corporation of San Jose, Calif. has a CDR circuit. The Stratix II GX CDR circuit includes a bang-bang phase detector circuit, a charge pump circuit, a loop filter circuit, and a voltage-controlled oscillator (VCO) circuit that are coupled into a loop.
The input latch of the bang-bang phase detector (BBPD) is implemented using thin-oxide transistors that receive a supply voltage of 1.2 volts. The charge pump and the VCO receive a 3-volt supply voltage to obtain a large control voltage range for the VCO. Thick-oxide transistors in the charge pump and VCO blocks function with a 3-volt supply voltage. The charge pump has a level-shifter that converts 1.2-volt UP and DN control signals generated by the phase detector to 3-volt signals.